Semiconductor circuits formed on semiconductor chips, or wafers, include a number of types of circuit elements, including, for example, resistors, capacitors, inductors, transistors, etc. These elements must be created on the semiconductor chip in a way that the value or performance of the element meets the requirements of the circuit in which they are included.
Any semiconductor material has certain characteristics, and some of these are such that an element constructed on the semiconductor will have a certain value that depends in whole or part upon the area occupied by the element. A number of elements, including resistors, capacitors and inductors, are thus typically created as geometric shapes of a size that, given the characteristics of the semiconductor, will result in a particular specified value.
In particular, certain designs require the use of such elements that are arbitrarily different in value but have a particular ratio. For example, to achieve a gain of 3.33, an operation amplifier may be configured in a so-called virtual ground configuration with a 1000 ohm (Ω) resistor and a 3,330Ω resistor (or 3.33 kilohms (kΩ); 1000Ω=1 kΩ). One known way of achieving this is to use a resistor of a given width and length for the input 1 kΩ resistor (the sheet resistance of the semiconductor material will determine the area of the resistor), and another resistor of the same width but 3.33 times the length of the 1 kΩ resistor for the 3.33 kΩ feedback resistor.
One of skill in the art will appreciate certain problems inherent in such construction. For example, the physical dimensions of an element are susceptible to errors or variations in the manufacturing process, which may not be able to reliably or repeatedly make the precise dimensions determined to yield the desired value for the resistor. Even small errors in the dimensions of the desired 1 kΩ and 3.33 kΩ resistors in the above example may result in significant differences in their actual resistances and, more importantly, in the ratio between them. While such dimensional errors may seem small, they may be enough to degrade the accuracy or performance of the circuit on the semiconductor chip.
Still further, in building elements on a semiconductor chip, it is necessary to make connections to the material. For example, to build a poly-silicon resistor on a chip there must be contact holes, and sometimes different doping levels at each end, for the metal traces to make good contact. The contact holes and associated features introduce an “end effect,” which is typically an unwanted additional resistance in series with the intended resistance, and is thus to be added to the value of the resistance as designed. This additional resistance generally depends largely upon how accurately the contact holes are cut in the chip material; it also creates a difference or error from the desired value, creating a resistance higher than intended, and makes it hard to match dissimilar values precisely since the unwanted end effect resistance may not be precisely known.
Again, in the example above, if two resistors are built to precise sizes to result in one resistor being 1 kΩ and the other being 3.33 kΩ, if the “end effect” adds, for example, 100Ω to each value, then the ratio between what are effectively a 1.1 kΩ resistor and a 3.43 kΩ resistor becomes 3.118 rather than the desired 3.33, an error of almost 7 percent. Again, this may significantly alter the desired performance of the circuit. These issues make it difficult to implement elements on semiconductor chips having precise values, and more specifically to implement multiple elements with precise ratios between their values.
One possible solution is provided in U.S. Pat. No. 8,453,097 (hereafter “the '097 patent”), commonly assigned to the assignee of the present application, which in some embodiments contemplates constructing a specified circuit element of arbitrary value as a compound element made from a number of nominally identical impedance elements. As explained therein, such a construction may reduce or eliminate many of the problems described above.
However, it must still be determined where to locate the nominal elements of such a compound element on a potential chip and how to connect them. Automated tools, such as “place and route tools” from, for example, Cadence or Synopsys, may be used to try to optimize the location and interconnection of the elements. However, these tools will normally consider the nominally identical elements as all separate elements to be placed, and may locate them in a way that causes certain undesirable phenomena, such as capacitive coupling or stray capacitance to a bulk node, if the place and route tool follows the industry standard “congestion based” placement.
Accordingly, a better way of optimizing the placement and routing of the nominally identical elements contained within compound elements is desirable.